Technical Field
The present invention relates to an electrical connecting structure, and more specifically, to an electrical connecting structure between a substrate and a semiconductor chip.
Description of the Related Art
FIG. 1 shows an example of a conventional electrical package 50 for optical communication. FIG. 1 shows a part of a cross-sectional diagram of the electrical package 50. The electrical package 50 includes a substrate 1, a semiconductor chip 2 electrically connected to the substrate 1 using an electrical connecting structure which includes a solder 5 and a Cu pillar 6 (Cu bump). A metal pad 4 formed in an insulating layer 3 on the substrate 1 electrically connects to a contact pad 8 formed in an insulating layer 7 on the semiconductor chip 2 via the electrical connecting structure.
The electrical package 50 further includes a pedestal 9 on the insulating layer 3 on the substrate 1 and an optical waveguide 10. The optical waveguide 10 is aligned with a light input/output port 11 formed at the side surface of the semiconductor chip 2. The semiconductor chip 2 includes a light emitting device (for example, laser diode, LED)/light receiving device (for example, photo diode). As shown by the arrow 12, light passes through between the light input/output port 11 and the optical waveguide 10.
In the conventional electrical package 50, when the position in z-direction (perpendicular direction) of the semiconductor chip 2 and the optical waveguide 10 is different by several micrometers (μm), the light coupling efficiency reduces. For example, when inter-metallic compounds (IMCs) are generated between the Cu bump of the semiconductor chip 2 and the metal pad 4 on the substrate 1, it is very difficult to control the thickness of IMCs and the Z-position of the semiconductor chip 2 and of the optical waveguide 10, which tends to vary by several μm.
Also, in mobile applications, thinner packages are required. Under these circumstances, the short joint height between the semiconductor chip 2 and the substrate 1 can potentially contribute to thinner packages. But, in the short joint height, the effect of volume shrinkage during IMCs formation becomes prominent, and it tends to generate cracks in the joint at thermal cycle (stress).
Therefore, it is necessary to control the electrical connecting structure between the substrate 1 and the semiconductor chip 2 in order to control, for example, the Z-position of the semiconductor chip 2 and the optical waveguide 10.